This application claims the benefit of Japanese Patent Application No. 2001-269636, filed Sep. 6, 2001 and incorporated herein by reference.
1. Field of the Invention
The present invention relates to a process for fabrication of semiconductor devices typified by memory LSI and system LSI. More particularly, the present invention relates to a process for efficiently forming a gate electrode of CMOS in a reduced length below 50 nm which is beyond the limit of lithography resolution.
2. Description of the Related Arts
Semiconductor devices fall under two broad categories: memory LSI typified by DRAM and logic LSI (or system LSI) typified by microprocessor (MPU). They are fabricated by several steps, including the formation of a gate electrode. This step consists of forming a gate insulating film, forming a gate electrode film, forming a mask layer, transferring a circuit pattern to the mask layer, etching the gate electrode film, ashing a resist and removing residual halogen gas, and removing (or cleaning) foreign matter (particles) resulting from etching. After the gate electrode has been formed, source and drain regions are formed.
The film-forming step differs in detail depending on the construction of the gate electrode. Usually, the gate insulating film is a thin SiO2 film, and the gate electrode film is a single layer of n-poly-Si or p-poly-Si or a multiple layer of WSi/poly-Si or W/WN/poly-Si. The etching of these films needs an etching mask to which a circuit pattern has been transferred.
The etching mask varies in material and thickness depending on the resolution and the feature size required. For example, requirements for the 0.5-xcexcm technology node were readily fulfilled by using a conventional resist and an exposure system with a mercury lamp emitting i-line (365 nm in wavelength) light. However, requirements for the 0.18-xcexcm technology node are met only by using a resist of multi-layer structure (having an antireflection coating film at the bottom) and an exposure system with KrF laser (248 nm in wavelength) and phase-shift mask for ultrahigh resolution. The antireflection coating film may be an organic one (BARC: Bottom Anti-Reflective Coating) or inorganic one (BARL: Bottom Anti-Reflective Layer). FIG. 2(a) is a sectional view of a sample which was taken just after exposure. This sample has an etching mask consisting of resist (201) and BARC (202) and a multi-layer film consisting of poly-Si (203) and SiO2 (204) on a silicon substrate (205). FIG. 2(b) is also a sectional view of a sample which was taken just after exposure. This sample has an etching mask consisting of resist (201) and BARL (207) and a multi-layer film consisting of poly-Si (203) and SiO2 (204).
The BARC film (202) is formed by spin coating in the same way as resist film is formed. It flattens over the step (209) that occurs as the result of shallow trench isolation (206). This flat film is suitable for high-resolution exposure with a small depth of focus. This advantage, however, is offset by the disadvantage involving difficulties in controlling dimensions at the time of etching the BARC film (202) because the amount of overetching differs between the thin part (210) and the thick part (211). On the other hand, the BARL film (207) is composed of such elements as Si, O, and N, and it is formed by CVD such that the resulting film has a uniform thickness along the step on the underlayer. In dry etching, this film gives a uniform amount of overetching and permits easy dimensional control for BARL etching. Unfortunately, from the standpoint of the exposure system, this film is detrimental to resolution on account of the limited depth of focus.
A common procedure to form the mask is as follows. First, the BARC film (202) and the resist film (201) are sequentially formed or the BARL film (207) and the resist film (201) are sequentially formed. Then, after exposure, the BARC film (202) or the BARL film (207) is patterned by dry etching.
There is another type of mask (hard mask) to be used for gate electrode etching. This mask is free of organic matter so that it improves the dimensional accuracy at the time of gate forming and it permits the wide selection of gate insulating film. The hard mask is an SiO2 film or SiN film made from TEOS(Tetra-Ethyl-Ortho-Silicate), HLD (High temperature Low pressure Decomposition), etc. FIG. 2(c) is a sectional view of a sample with a hard mask which was taken just after exposure. The hard mask is usually formed in the following way. The TEOS film (208), the BARC film (202), and the resist film (201) are sequentially formed. After exposure, the BARC film (202) and the TEOS film (208) are patterned by dry etching. Finally, the resist film (201) and the BARC film (202) are removed by ashing. The dry etching and ashing in this procedure are accomplished by using special equipment.
The dry etching used for mask forming and gate etching is usually accomplished by an ion-assisted reaction which involves ions (which occur in plasma generated from a reactant gas in a vacuum chamber) and neutral radicals. A common way to generate plasma is to irradiate the reactant gas (introduced into a vacuum chamber for etching) with electromagnetic waves for dissociation. Typical plasma sources include capacitive coupled plasma (CCP), inductive coupled plasma (ICP), and electron resonance plasma (ECR). CCP and ICP employ electromagnetic waves of 13.56 MHz or 27 MHz, and ECR employs microwaves of 2.45 GHz or UHF of 450 MHz.
The dry etching apparatus with a plasma source is operated by controlling the following parameters so that the etched film has desired dimensions: the species of etchant gas, the processing pressure, and the electromagnetic power, which determine the characteristics of plasma; the sample temperature which determines the characteristics of chemical reactions; and the power of RF bias to draw ions to the sample. The object of etching one kind of film for mask forming and another kind of film for gate etching is achieved by selecting an etchant gas and an apparatus suitable for respective etching reactions. For example, the etching of BARC film for mask forming is carried out by using an etching apparatus with CCP plasma source in which O2 is mixed with CF4 or N2 and plasma is generated from a gas diluted with Ar. Also, the etching of BARL or SiO2 is carried out by using an etching apparatus with CCP plasma source in which plasma is generated from a fluorocarbon gas (such as C4F8 and C5F8) diluted with O2 and CO diluted with Ar. The etching of the gate electrode is carried out by using an etching apparatus with ICP or ECR plasma source. The etching of W layer or WSi layer employs CF4 or SF6 incorporated with Cl2, N2, and O2. The etching of poly-Si layer employs plasma generated from Cl2, HBr, or NF3 incorporated with O2 or He.
Ashing to remove the resist and halogen remaining after etching employs plasma generated from O2 by ICP or microwave or employs O3 generated under normal pressure. (In the former case, reactions are controlled by the sample temperature.) There may be an instance where reactions with the resist are accelerated by incorporating O2 with a fluorocarbon gas such as CF4 and CHF3.
The cleaning step to remove foreign matter and contaminants resulting from etching is accomplished mainly by wet cleaning with a solution, such as aqueous solutions of NH4OH/H2O2, HCl/H2O2, and hydrofluoric acid. The mixing ratio, treating time, and solution temperature may be adequately controlled according to the kind of contaminant.
After the gate electrode has been formed, the source and drain are formed in the following manner, reference being made to FIGS. 3(a) and 3(b) which exemplify the case of using a hard mask. First, as shown in FIG. 3(a), a lightly doped extension (304) is formed by ion implantation which employs the gate electrode as a mask. Second, as shown in FIG. 3(b), a sidewall spacer (307) is formed by deposition and ensuing etching, and a heavily doped extension (308) is formed by ion implantation. The TEOS layer, polysilicon gate electrode film, SiO2 gate insulating film, and silicon substrate are designated as (301), (302), (303), and (305), respectively.
The gate electrode formed by the above-mentioned process has been decreasing in size year after year in order to meet requirements for lower power consumption and higher speed. The recent issue of ITRS (International Technology Roadmap for Semiconductors, 2000, SC.2) predicts that the technology node will be reduced more than that shown in the previous issue, as shown in Table 1.
Moreover, advanced semiconductor manufacturers are planning new products to be shipped in 2001 and 2003, which will have a gate length of 70 nm and 50 mm, respectively. These values are ahead of predictions by ITRS. FIG. 4(a) shows a prediction of the decreasing gate length and its corresponding critical dimension over a few years to come. According to this prediction, the critical dimension in 2003 will be 100 nm (as indicated by line 401) and the MPU gate length will be 50 nm (as indicated by line 402). This means that as much trimming as 50 nm is necessary. The critical dimension shown in FIG. 4(a) is based on the assumption that ArF laser (193 nm in wavelength), which is regarded as the new-generation technology, will be used for exposure in 2003 and afterward. At present, however, this new technology is not yet in practical use because of problems with resist materials, exposure characteristics, and apparatus cost.
Up to now, semiconductor manufacturers have attempted to realize small dimensions beyond the limit of exposure by trimming with an etching apparatus (after exposure with an existing exposure tool) or by contriving the mask structure and process flow. For example, in the case where the gate electrode is formed with the help of BARC film as shown in FIGS. 2(a) and 2(c), it has been common practice to perform trimming on both the resist and the BARC mask at the time of BARC etching. Since BARC has a composition similar to that of resist, the trimming of the resist can be accomplished by using the plasma of gas (composed of O2, CF4, N2, and Ar) used for BARC etching.
There are other ways for trimming, such as contriving the mask structure or process flow, performing trimming on the resist, and performing trimming on the gate electrode. Contriving the mask structure or process flow is disclosed in Japanese Patent Laid-open Nos. 209018/1994 and 136402/1993. The former is concerned with a method of forming a miniaturized gate which consists of forming film and performing side etching on dummy L/S (line and space) of SiO2. The latter is concerned with a method of trimming by performing side etching on a specific mask layer of a multi-layered mask.
In addition, Japanese Patent Laid-open No. 78400/1996 discloses a technology for trimming both the mask and the gate electrode simultaneously by treating them with an SFx gas in the same chamber under the same condition. In the case where the BARL film is used as shown in FIG. 2(b), the resist is trimmed directly by using an ashing apparatus that employs ICP or O3. A method of trimming the gate electrode is disclosed in Japanese Patent Laid-open No. 22396/1995. This method is concerned with trimming the WSi/poly-Si multi-layered gate. Some new technologies have recently be publicized which are concerned with the trimming of the single-layered gate electrode. They achieve the object of trimming the gate electrode by forming notches near the interface with the underlying oxide film (described in IEDM 1999 and Society of Applied Physics 2001 Spring), by utilizing the steps of forming a protection film with O2 and side etching (described in Dry Process Symposium 2000), and by forming notches with an H-containing gas such as HCl and HBr (described in ICMI 2001).
If the critical dimension decreases as predicted in FIG. 4(a) (line 401), it would be necessary to reduce the thickness of the resist film accordingly. The resist film necessary for exposure of fine patterns will decrease in thickness as predicted in FIG. 4(b). For resolution of a 100-nm line, the resist film should be thinner than 300 nm. This requirement arises from the fact that the thickness of resist film needs to be less than approximately three times the magnitude of resolution so that the pattern will not be destroyed after exposure by the surface tension of the developing solution. However, the antireflection coating film remains unchanged in thickness even though miniaturization proceeds as shown in FIG. 4(a), because its thickness is precisely determined by its ability to absorb and interfere with exposure light of specific wavelength. Likewise, the gate electrode will have a limit to reduction in its thickness, which is approximately 100 nm. This is because reduction in voltage for dopant implantation is limited and there is possibility of dopant penetrating the gate insulating film due to heat diffusion.
It follows that although the resist film for exposure decreases in thickness (as indicated by line 404) as the gate electrode decreases in length, the films (such as BARC, BARL, hard mask, and gate electrode) to be etched remain unchanged in thickness. For example, line 405 shows the residual thickness of the resist mask after the BARC etching. Line 403 shows the residual thickness of the resist mask necessary for etching the gate electrode. This will pose a problem in 2003 that the thickness of the resist film necessary for etching (indicated by line 403) is insufficient if the resist trimming is accomplished after the BARC etching. See FIG. 4(b). Also in the case of the sample with BARL as shown in FIG. 2(b), a similar consequence is foreseen from the estimated thickness necessary for etching BARL and poly-Si. In addition, referring to FIG. 5, trimming by BARC etching alone poses a problem with breakage because there is a difference in the amount of overetching between the upper part (503) and the lower part (505) of the step resulting from STI (shallow trench isolation), as schematically shown in the figure. This difference prevents uniform trimming by 50 nm and excess trimming takes place at the step (502) where the amount of overetching is large and the BARC film is thinnest.
On the other hand, the method disclosed in Japanese Patent Laid-open Nos. 209018/1994 and 136402/1993 (mentioned above), which is designed to achieve trimming by contriving the mask structure and process flow, has the disadvantage of increasing the chip cost and decreasing the total throughput due to increased steps. The method disclosed in Japanese Patent Laid-open No. 78400/1996 does not meet requirements for ever-decreasing resist thickness because if the gate electrode is to be anisotropically etched with an F-based gas used for resist trimming, it is necessary to apply an RF bias which also brings about anisotropic etching in the direction of resist thickness. Another disadvantage of this method is that trimming of the mask proceeds faster than trimming of the gate electrode and hence the gate electrode tends to assume a forwardly tapered shape and there are difficulties in controlling critical dimensions (CD). In the meantime, it would be difficult to achieve trimming of the gate electrode by as much as 50 nm in view of the fact that the SiO2 layer becomes as thin as approximately 1 nm. So long as trimming resorts to side etching with high selectivity for the underlayer, an amount of trimming as much as 20-30 nm would be a limit without underlayer loss.
Moreover, the conventional method, which consists of performing resist trimming, BARC trimming, and gate electrode trimming in different apparatuses and transferring wafers from one apparatus to another in the atmosphere, poses a problem with contamination from the apparatus and the atmosphere. One way to tackle this problem is to add a cleaning step; however, this in turn poses another problem with decrease in throughput and increase in production cost due to additional COO (cost of ownership). Further, referring to FIG. 6(a), it is reported that resist (602) exposed to ArF laser is subject to surface roughening on the side wall as indicated by (601). This surface roughness should be reduced to prevent the variation of gate dimensions.
The present invention was completed with the foregoing problems taken into account. It is an object of the present invention to provide an etching process for gate electrodes as short as 50 nm, exceeding the limit of exposure.
According to the present invention, it is possible to solve the problem arising from the ever-decreasing thickness of the resist to meet requirements for miniaturization anticipated in 2003 onward and the problem with insufficient trimming of the gate electrode which occurs if underlayer loss is to be avoided. These problems are solved by using, in combination, gate electrode trimming with high resist selectivity and trimming at the time of mask forming.
According to the present invention, it is possible to reduce variation in trimming and to realize high-precision processing. These objects are achieved by reducing the difference in the amounts of overetching at the step arising from the STI process by minimizing the amount of overetching for BARC trimming. Variation in dimensions at the time of BARC etching due to the step arising from STI occurs because the amount of trimming increases on account of insufficient reaction products produced during overetching for BARC trimming. In other words, difference in the amount of overetching causes variation in the amount of trimming.
According to the present invention, it is possible to solve problems arising from ever-increasing complexity in the process for fabrication of semiconductor devices, because the process of the present invention does not need any special mask structure or any change in gate structure.
According to the present invention, it is possible to solve the problems with contamination by foreign matter that occur while wafers are being transferred from one apparatus to another. (Contamination is the major cause to decrease yields.) The solution is achieved by performing mask trimming and gate electrode trimming in a vacuum environment.
According to the present invention, it is possible to solve the problems with decrease in throughput, disposal of washing solution, and increase in cost of ownership (COO), all of which result from the additional cleaning step. This object is achieved because the process of the present invention permits dry cleaning to be performed in a vacuum environment. Dry cleaning in this manner prevents the water absorption of hydrogen halide compounds remaining after dry etching. This permits the wet cleaning to be eliminated or simplified.
According to the present invention, it is possible to control dimensions highly accurately and to realize very small gates (on the order of 50 nm) in high yields. This object is achieved by carrying out the step of inspecting dimensions or contamination in a vacuum environment and feeding the results of inspection to the subsequent steps for their adjustment.
According to the present invention, it is possible to solve the problem with the roughening of resist film patterned by ArF laser. This object is achieved by not exposing wafers to the atmosphere, because the problem arises from hydrolysis in the atmosphere as shown at (603) and (604) in FIG. 6(b).